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1 ? fn7327.3 el4501 video front end the el4501 is a highly-integr ated video front end (vfe) incorporating all of the key si gnal conditioning functions for analog video signals. it provides a flexible front-end interface for analog or analog/digital video sub-systems. the vfe contains a high bandwidth dc-restore, an advanced sync separator and a data slicer with an adjustable threshold, configurable output and power-down mode. the vfe performs restoration of the dc level (blanking level) of a video signal and the recovery of all signal timing necessary for synchronization and control. additionally, data embedded in the active video or vbi regions of the video signal may be extracted using the flexible data slicer incorporated into the vfe. the advanced sync separator exhibits excellent noise immunity by incorporating a digital brick wall filter and signal qualification algorithm. the dc-restored video amplifier is unity gain stable with an unloaded -3db bandwidth of 100mhz. the input common mode voltage range extends from the negative rail to within 1.5v of the positive rail. when driving a 75 double terminated coaxial cable, the amplifier can drive to within 150mv of either rail. with 200v/s slew rate, the amplifier is well suited for composite and component video applications. the vfe operates from a single 5v supply from -40c to +85c and is available in a reduced footprint 24 ld qsop package. features ? dc-restore and sync separator ? wideband (100mhz) dc-restore ? advanced sync separator ? programmable data slicer ? single 5v operation ? diff gain/phase = 0.05%/0.03, r l = 10k , a v = 1 ? low power (<75mw) ? pb-free plus anneal available (rohs compliant) applications ? video capture & editing ? video projectors ? set top boxes ? security video ? embedded data recovery pinout el4501 (24 ld qsop) top view ordering information part number part marking tape & reel package pkg. dwg. # el4501iu el4501iu - 24 ld qsop mdp0040 el4501iu-t7 el4501iu 7? 24 ld qsop mdp0040 EL4501IU-T13 el4501iu 13? 24 ld qsop mdp0040 el4501iuz (see note) el4501iuz - 24 ld qsop (pb-free) mdp0040 el4501iuz-t7 (see note) el4501iuz 7? 24 ld qsop (pb-free) mdp0040 el4501iuz-t13 (see note) el4501iuz 13? 24 ld qsop (pb-free) mdp0040 note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 vfb video in ds mode ds enable gnd gndd rfreq fsel sync in los composite horizontal video out ds out ds ref ref in ref out vs vsd sync amp slice mode back porch odd/even vertical data sheet november 12, 2010 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright ? intersil americas inc. 2003-2004, 2006, 2010. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = 25c) supply voltage (v s to gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6v pin voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .gnd -0.3v, v s +0.3v storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . 125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves maximum continuous current (video out) . . . . . . . . . . . . . 50ma caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v s = v sd = 5v, gnd = 0v, t a = 25c, input video = 1v p-p , r freq = 130k parameter description conditions min typ max unit i sa input supply current no load 7.5 10.5 13.5 ma i sd digital supply current no load, v in = 0v 1.9 2.3 4 ma v s input supply voltage range 4.5 5.5 v v sd digital input supply voltage range 4.5 5.5 v video amplifier section v op positive output voltage swing (video out) (note 1) r l = 150 to v s /2 4.65 4.70 v r l = 150 to gnd 4.20 4.60 v r l = 1k to v s /2 4.85 4.90 v v on negative output voltage swing (video out) (note 1) r l = 150 to v s /2 0.15 0.30 v r l = 150 to gnd 0.06 0.25 v r l = 1k to v s /2 0.05 0.20 v +i out positive output current (video out) r l = 10 to v s /2 60 70 ma -i out negative output current (video out) r l = 10 to v s /2 -50 -60 ma dg differential gain error (video out) (note 2) a v = 1, r l = 10k , r f = 0 0.05 % dp differential phase error (video out) (note 2) a v = 1, r l = 10k , r f = 0 0.03 bw bandwidth -3db, g = 1, r l = 10k to gnd, r f = 0 100 mhz -3db, g = 1, r l = 150 to gnd, r f = 0 60 mhz bw1 bandwidth 0.1db, g = 2, r l = 150 to gnd 8 mhz sr slew rate 25% to 75%, 3.5v p-p , r l = 150 , r f = 0 80 96 v/s v rl ref level range 0/3.5 v t s settling time to 0.1%, v in = 0v to 3v 35 ns r in input resistance (video in) 115 k c in input capacitance (video in) 1.5 pf a vol open loop voltage gain r l = no load, v out = 0.5v to 3v 65 db r l = 150 to gnd, v out = 0.5v to 3v 50 db dc-restore section cmir common mode input range (ref in) 0/3.5 v v os input offset voltage dc restored 20 mv tcv os input offset voltage temperature coefficient 10 v/c i b input bias current (ref in) v cm = 0v to 3.5v -10 0.001 10 a el4501
3 v ref reference output voltage (ref out) i out = +2ma to -0.5ma 1.15 1.3 1.4 v i rmax available restore current (vfb) 18.5 a data slicer section i ih input high current (ds mode & ds enable) v ih = 5v 6 10 a i il input low current (ds mode & ds enable) v il = 0v 200 350 na v ih input high voltage (ds mode & ds enable) 4.5 v v il input low voltage (ds mode & ds enable) 0.5 v v oh output high voltage (ds out) i out = -1ma 4.75 4.9 v v ol output low voltage (ds out) i out = +1ma 0.1 0.25 v i out short circuit current (ds out) r l = 10 to 2.5v 8 11 ma i b input bias current (ds ref) ds ref = 0v to 5v -10 0.001 10 a v os input offset voltage -20 +20 mv v hys hysteresis 5 mv t pd propagation delay 50% to 50% 18 ns t r/f rise/fall time 10% to 90%, r l = 150k , c l = 5pf 1.2 ns sync separator section z source (max) maximimum source impedance driving sync in 1000 i ih input high current (fsel & sync mode) v ih = 5v -1 1 a i il input low current (fsel & sync mode) v il = 0v -1 1 a v ih input high voltage (fsel & sync mode) 4.5 v v il input low voltage (fsel & sync mode) 0.5 v v oh output high voltage i oh = -1.6ma 4.6 v v ol output low voltage i ol = +1.6ma 0.4 v v thrsha adaptive slice level sync mode = 0v 40 50 60 % v thrshf fixed slice threshold slice mode = v s 80 100 120 mv v si sync in reference voltage 1.8 v r insi sync in input impedance 115 k v range input dynamic range 0.5 2.0 v p-p t cd composite delay fsel = 0, from 50% of sync leading edge 25 35 45 ns t cdf composite delay fsel = 1, from 50% of sync leading edge 150 225 280 ns t bd back porch delay fsel = 0, from 50% of trailing sync edge 125 170 225 ns t bdf back porch delay fsel = 1, from 50% of trailing sync edge 250 420 550 ns t hd horizontal delay fsel = 0/1, from 50% of sync leading edge 365 470 585 ns t bw back porch width fsel = 0/1 2.8 3.2 4.1 s t hw horizontal width fsel = 0 1.1 1.3 1.5 s t hwf horizontal width fsel = 1 1.2 1.5 1.8 s t vw vertical width fsel = 0/1, standard ntsc 196 198 200 s t vdd vertical default delay fsel = 0 26.5 31.2 35.9 s t vddf vertical default delay fsel = 1 31.5 s electrical specifications v s = v sd = 5v, gnd = 0v, t a = 25c, input video = 1v p-p , r freq = 130k (continued) parameter description conditions min typ max unit el4501
4 f h horiz scan rate 15 130 khz v lose analog los enable threshold minimum sync amplitude to enable outputs 120 mv v losd analog los disable threshold maximum sync amplitude to disable outputs 80 mv t jit output jitter all sync separator outputs 5 ns a sa sync amp gain 1.7 2.0 2.3 r sa sync amp output impedance 200 v rfreq r freq reference voltage r freq = 13k to 130k 1.15 1.28 1.4 v notes: 1. r l is total load resistance due to feedback resistor and load resistor. 2. ac signal amplitude = 286mv pp , f = 3.58mhz, ref in is swept from 0.8v to 3.4v, r l is dc coupled. electrical specifications v s = v sd = 5v, gnd = 0v, t a = 25c, input video = 1v p-p , r freq = 130k (continued) parameter description conditions min typ max unit typical performance curves figure 1. non-inverting frequency response (gai n) figure 2. non-inverting frequency response (phase) figure 3. frequency response for various r l figure 4. frequency response for various c l 4 2 0 -2 -4 -6 100k 1m 10m 100m frequency (hz) normalized magnitude (db) v ref_in =1.3v r l =150 a v =1 r f =0 a v =5 r f =1k a v =2 r f =1k 45 0 -45 -90 -135 -180 phase () 100k 1m 10m 100m frequency (hz) v ref_in =1.3v r l =150 a v =1 r f =0 a v =5 r f =1k a v =2 r f =1k r l =10k 4 2 0 -2 -4 -6 100k 1m 10m 100m frequency (hz) normalized magnitude (db) v ref_in =1.3v r f =0 a v =1 r l =150 r l =1k 8 4 0 -4 -8 -12 normalized magnitude (db) 100k 1m 10m 100m frequency (hz) c l =39pf c l =15pf c l =0pf v ref_in =1.3v r f =150 a v =1 el4501
5 figure 5. frequency response for various r f figure 6. frequency response for various r l figure 7. frequency response for various c l figure 8. closed loop output impedance figure 9. open loop gain and phase vs frequency figure 10. psrr and cmrr vs frequency - video amp typical performance curves (continued) 4 2 0 -2 -4 -6 100k 1m 10m 100m frequency (hz) normalized gain (db) a v =2 r l =150 r f =2k r f =1k r f =500 4 2 0 -2 -4 -6 100k 1m 10m 100m frequency (hz) normalized gain (db) r l =10k r l =150 r l =75 a v =2 r f =1k c l =100pf v ref_in =1.3v r f =1k r l =150 a v =2 4 2 0 -2 -4 -6 100k 1m 10m 100m frequency (hz) normalized magnitude (db) c l =68pf c l =0pf c l =15pf c l =47pf 100 10 1 0.1 10k 100k 1m 100m frequency (hz) impedance ( ) a v =1 r f =0 10m 90 70 50 30 10 -10 1k 10k 1m 100m frequency (hz) gain (db) 0 -45 -90 -135 -180 -270 100k 10m phase () gain r l =10k gain r l =150 phase r l =10k phase r l =150 10 -10 -30 -50 -70 1k 10k 1m 100m frequency (hz) psrr, cmrr (db) 10m 100k cmrr psrr v s psrr v sd el4501
6 figure 11. voltage noise vs frequency - vi deo amp figure 12. differential gain for r l tied to 0v figure 13. differential phase for r l tied to 0v figure 14. differential gain for r l tied to 0v figure 15. differential phase for r l tied to 0v figure 16. acquisition time vs hold capacitance typical performance curves (continued) 10k 1k 100 10 10 100 10k 100m frequency (hz) voltage noise (nv/ hz) 1m 1k 100k 10m 0.25 0.15 0 -0.1 0.5 1 1.5 3.5 v out (v) differential gain (%) 2.5 23 r f =0 a v =1 0.2 0.05 -0.05 0.1 r l =150 r l =10k 0.08 -0.04 -0.12 0.5 1 1.5 3.5 v out (v) differential phase () 2.5 23 0 -0.08 0.04 r f =0 a v =1 r l =150 r l =10k 0.5 0.1 -0.2 0.5 1 1.5 3.5 v out (v) differential gain (%) 2.5 23 0.3 -0.1 0.4 0 0.2 r f =1k a v =2 r l =150 r l =10k 0.15 -0.15 -0.35 0.5 1 1.5 3.5 v out (v) differential phase () 2.5 23 -0.05 -0.25 0.05 r f =1k a v =2 r l =150 r l =10k 1600 0 0 100 200 500 hold capacitance (pf) acquisition time (s) 300 400 800 400 1200 a v =2 r f =1k r l =150 v in =1v step v ref_in =13.v el4501
7 figure 17. dc offset voltage at v out vs v ref_in figure 18. dc-restore current vs temperature figure 19. droop current vs temperature figure 20. hold step voltage vs hold capacitance figure 21. droop rate vs hold capac itance figure 22. line rate vs r freq typical performance curves (continued) 25 10 0 00.5 1.5 4 v ref_in (v) offset voltage (mv) 3 2.5 3.5 15 5 20 12 25 10 0 -40 -20 20 100 temperature (c) restore current (a) 80 60 15 5 20 040 10 0.001 -40 -30 30 80 temperature (c) droop current (na) 50 40 60 0.1 1 0.01 10 70 020 -20 -10 90 i droop =c h *( v ramp / t) 10 0.01 110100 hold capacitance (pf) hold step voltage (mv) 0.1 1 1k v= q/c h 100 0.01 110100 hold capacitance (pf) droop rate (mv/ms) 1 10 0.1 1k dr= v ramp / t 160 140 120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 r freq (k ) line rate (khz) el4501
8 figure 23. line rate vs r freq figure 24. back porch and horizontal sync width vs r freq figure 25. delay time vs r freq figure 26. composite delay vs temperature - fsel = 0 figure 27. composite delay vs temperature - fsel = 1 figure 28. horizontal delay vs temperature typical performance curves (continued) 160 140 120 100 80 60 40 20 0 10 100 200 r freq (k ) line rate (khz) 4 3.5 3 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 120 140 r freq (k ) back porch width, horizontal sync width (s) back porch horizontal (fsel=1) horizontal (fsel=0) 600 500 400 300 200 100 0 0 20 40 60 80 100 120 140 r freq (k ) delay time (ns) horizontal back porch (fsel=1) back porch (fsel=0) 44 34 -40 20 60 temperature (c) composite sync delay (ns) 36 40 100 42 20 80 040 38 r freq =130k 244 224 -40 20 60 temperature (c) composite sync delay (ns) 228 236 100 240 20 80 040 232 r freq =130k 500 470 -40 20 60 temperature (c) horizontal sync delay (ns) 475 485 100 495 20 80 040 480 490 r freq =130k el4501
9 figure 29. data slicer delay vs temperature - ds mode = 1 figure 30. back porch delay vs temperature - fsel = 0 figure 31. back porch delay vs temperature - fsel = 1 figure 32. back porch width vs temperature figure 33. vertical sync width vs temperature figure 34. package power dissipation vs ambient temperature typical performance curves (continued) 35 30 -40 20 60 temperature (c) data slicer delay (ns) 31 33 100 20 80 040 32 34 r freq =130k 182 168 -40 20 60 temperature (c) back porch delay (ns) 170 178 100 20 80 040 174 180 176 172 r freq =130k 440 410 -40 20 60 temperature (c) back porch delay (ns) 415 100 20 80 040 425 435 430 420 r freq =130k 3.72 3.58 -40 20 60 temperature (c) back porch width (s) 3.6 100 20 80 040 3.68 3.7 3.62 3.66 3.64 r freq =130k 210 150 -40 20 60 temperature (c) vertical sync width (s) 160 100 20 80 040 190 200 180 170 r freq =130k jedec jesd51-3 low effective thermal conductivity test board 1.4 0 1 0.6 0.4 0.2 power dissipation (w) 1.2 0.8 0125 100 75 50 25 ambient temperature (c) 150 85 870mw j a = 1 1 5 c / w q s o p 2 4 el4501
10 timing diagrams figure 35. package power dissipation vs ambient temperature typical performance curves (continued) jedec jesd51-7 high effective thermal conductivity test board 1.4 0 1 0.6 0.4 0.2 power dissipation (w) 1.2 0.8 0125 100 75 50 25 ambient temperature (c) 150 85 1.136w j a = 8 8 c / w q s o p 2 4 fields one and three (odd) composite signal fields two and four (even) composite signal composite sync output burst/back porch output horizontal sync output vertical sync output odd/even output composite sync output burst/back porch output horizontal sync output vertical sync output odd/even output el4501
11 timing diagrams standard (ntsc input) h. sync detail video in burst/back porch output horizontal sync output composite sync output t cd t bd t hd t bw t hw video in vertical sync output odd/even t cd +t t cd +2t t<< t cd t bw t cd el4501
12 pin descriptions pin number pin name pin type pin description equivalent circuit 1 vfb input connection for gain and feedback resistors, r f and r g circuit 1 2 video in input input to dc-restore amplifier; input coupling capacitor connects from here to video source circuit 2 3 ds mode input sets the mode of the ds comparator; logic low selects a standard logic output; logic high selects an open drain/collector circuit 3 4 ds enable input enables the output of the comparator; a logic high enables the comparator; a logic low three-states it circuit 4 5 gnd input analog ground 6 gndd input digital ground 7 rfreq input connection for bias resistor that sets the overall timing circuit 5 v s gnd v s gnd v s gnd v s gnd v s gnd el4501
13 8 fsel input enable/bypass internal br ick wall filter; a logic high is used to enable the filter; a logic low to disable it circuit 6 9 sync in input input to the sync separator; connects to the video source via a coupling capacitor or to a color burst input filter circuit 7 10 los output loss of signal output; goes high if no input video signal is detected circuit 8 11 composite output composite sy nc output reference circuit 8 12 horizontal output horizontal sync output reference circuit 8 13 vertical output vertical sync output reference circuit 8 14 odd/even output odd/even field i ndicator output reference circuit 8 15 back porch output back porch output reference circuit 8 16 slice mode input low = 50% slicing level; high = 70mv fixed slicing le vel reference circuit 8 17 sync amp output amplitude of sync tip; can be used to control agc circuit circuit 9 18 vsd input digital power supply; nominally +5v circuit 10 19 vs input analog power supply; nom inally +5v reference circuit 10 pin descriptions pin number pin name pin type pin description equivalent circuit v d gnd v d gnd gnd v s v s gnd gnd v sd v s el4501
14 20 ref out output voltage reference for use as blanking level in low cost system circuit 11 21 ref in input dc voltage on this pin sets the dc-restore voltage and output blanking level circuit 12 22 ds ref input sets the slicing level or reference level for the comparator circuit 13 23 ds out output output of the data slicing comparator; the output is either open drain or st andard symmetrical logic depending on the ds mode pin circuit 14 24 video out output output of dc-restore amplifier circuit 15 pin descriptions pin number pin name pin type pin description equivalent circuit v s gnd v s gnd v s gnd v s gnd v s gnd el4501
15 block diagram applications information product description the el4501 is a video front-end sub-system comprised of a video amplifier with dc-restore, an adjustable threshold data slicer, and an advanced sync separator. the prime function of the system is to dc-stab ilize and buff er ac-coupled analog video signals and to extract timing reference signals embedded in the video signal. an adjustable threshold data slicer incorporated into the el4501 may be used to extract data embedded within the active video or vbi regions of a video signal. theory of operation dc-restore loop when video signals are distributed, it is common to employ capacitive coupling to prevent dc current flow due to differences in local grounds or signal reference levels. however, the coupling capacitor causes the dc level of the signal post capacitor to be dependent on the video (luminance) content of the waveform. a dc-restore loop is used to correct this behavior by moving a portion of the video waveform to a dc reference level in response to a control signal. when the loop is operating, dc drift accumulates over a single line only, before it is corrected. the peak value of drift is limited by the rate of the control signal (typically video line rate) and the ac coupling time constant. the restore loop is comprised of a 100mhz forward video amplifier, combined with a nulling amplifier and sample and hold circuit. for maximum flexibility the hold capacitor is placed off-chip, allowing the loop response rate to be tailored for specific applications and minimizing hold-step problems. the loop provides a restore current peak of 20a at room temperature. figure 36 shows the amplifier and s/h connection. during normal operation the internally generated dc-restore control signal is timed to the back porch of the video waveform. figure 37 shows an ntsc video signal, along with the el4501 back porch output. in operation, back porch activates the s/h switch, completing the nulling feedback loop and driving the video amplifier output towards the reference voltage. at the end of back porch, the external capacitor holds the correction voltage for the remainder of the video line. in the absence of a valid input signal, the chip generates a repetitive, arbitrary restore control signal at the line rate set by the external resistor r freq . although uncorrelated to the input, the pulse - + - + - + filter + - sync separator gnd gnd d rfreq los sync amp fsel sync in video in 0.1f 0.1f input video v s v sd ds ref odd/even vertical horizontal composite back porch ref out ref in vfb video out ds out ds enable ds mode c hold c ref r f r g 1.3v track/ hold slice mode el4501
16 prevents the amplifier output drifting significantly from the dc-restore reference level. this improves start-up behavior and speeds recovery after a signal drop-out. for ease of use, the el4501 provides a buffered 1.3v dc level normally connected directly to the rest ore loop reference input (ref in). alternatively, an extern al voltage between 0v and 3.5v, connected to ref in, can be used to set the restored level. auto-zero loop bandwidth the gain bandwidth product (gbwp) of the auto-zero loop is determined by the size of the hold capacitor and the transconductance (g m 1) of the sample and hold amplifier. gbwp = g m 1/(2 * c h ), gm1 is about 1/(29k ), for c h = 270pf, gbwp is 20khz. for c h = 100pf, gbwp is about 55khz. charge injection and hold step error charge injection refers to the charge transferred to the hold capacitor when switching to the hold mode. the charge should ideally be 0, but due to stray capacitive coupling and other effects, it is typically 6f c. this charge changes the hold capacitor voltage by v = q/c h and will shift the output voltage of the video amplifier by v. however, this shift is small and can be negligible for the el4501 (see the hold step voltage error vs hold capacitance curve). assuming c h = 100pf, v is about 60v. there will be 60v change at the video amplifier output. droop rate when the s/h amplifier is in the hold mode, there is a small current that leaks from the switch to the hold capacitor. this quantity is called the droop current. this droop current produces a ramp in the hold capacitor voltage, which in turn produces a similar voltage at the video amplifier output. the droop rate at the video amplifier output can be found using the following equation: assuming c h = 100pf, from the droop rate vs hold capacitance curve, the droop rate is about 0.31mv/ms at the video amplifier output at r oom temperature. in ntsc applications, there is about 60s between auto-zero periods. thus, there is (0.31mv/ms) * 60s = 18.6v. it is much less than 0.5ire (3.5mv). this drift is negligible. choice of hold capacitor the el4501 allows the user to choose the hold capacitor as low as 1pf and it is still stable. a smaller hold capacitor has a faster acquisition time and faster auto-zero loop response, but would increase the droop and hold step error. also, if the acquisition time is too fast, it would probably give an image with clamp streaking and low frequency noise with noisy signals. increasing the hold capacitor would increase the acquisition time, lower the auto-zero loop response, lower the droop and hold step error. see the performance curves for the trade-off. normally, in video (ntsc and pal) applications, a smooth acquisition might takes about 10 to 20 scan lines. for a hold capacitor equal to 270pf, the acquisition time is about 10 lin es. in the worse case, ambient temperature is 85c, the dr oop current is 2.2na which causes the output voltage ramp to about 0.49mv for 60s. this drift is negligible in most applications. figure 38 shows the input and output waveforms of the video amplifier while the s/h is in sample mode. applying a 1v step to the video amplifier input, the output of the video amplifier jumps to 2.3v. then, the auto-zero syst em tries to drive the video output to the reference voltage, which is 1.3v. the acquisition time takes about 10 ntsc scan lines. - + - + s/h v ref_in v out v in 0.1f g m ~1.8v c h gbwp g m 2 c h --------------- = figure 36. dc-restore amplifier and s/h configuration input video signal back porch output ch1=500mv/div ch3=5v/div m=10s figure 37. ntsc video signal with back porch output drooprate v ramp t ------------------------ = video amp output video amp input c h =270pf auto-zero mechanism restores amplifier output to 1.3v after +1v step at input ch1=500mv/div ch2=1v/div m=100s figure 38. input and output waveforms with s/h in sample mode el4501
17 data slicer the data slicer is a fast comp arator with the output of the video amplifier connected to its inverting input and the ds ref connected to its non-inv erting input. the ds out is logical inverse of the video output sliced at the ds ref voltage. the propagation delay from the video amplifier output to the ds out is about 18ns. there is about 10mv hysteresis added internally in the comparator to prevent the oscillation at the ds out when the voltages at the two inputs are very close or equal. an adjustable ds ref voltage may be used to extract data embedded within the active video or video blanking interval regions of a video signal. logic low at the ds enable pin enables the comparator and logic low lets the ds out be three-state. the ds mode pin sets the m ode of the ds comparator. logic low at the ds mode pin selects a standard logic output and a logic high selects an open drain/collector output. video amplifier the el4501 dc-restore block incorporates a wide bandwidth, single supply, low power, rail-to-rail output, voltage feedback operational amplifier. the amplifier is internally compensated for closed loop feedback gains of +1 or greater. larger gains are acceptable but bandwidth will be reduced according to the familiar gain-bandwidth product. connected in a voltage follower mode and driving a high impedance load, the amplifier has a -3db bandwidth of 100mhz. driving a 150 load, the -3db bandwidth reduces to 60mhz while maintaining a 200v/s slew rate. choice of feedback resistor, r f the video amplifier is optimized for applications that require a gain of +1. hence, no fee dback resistor is required. however, for gains greater than +1, the feedback resistor forms a pole with the hold capacitance. as this pole becomes larger, phase margin is reduced. this causes ringing in the time domain and peaking in the frequency domain. therefore, r f has some maximum value that should not be exceeded for optimum performance. if a large value of r f must be used, a small capacitor in the few picofarad range in parallel with r f can help to reduce ringing and peaking at the expense of reducing the bandwidth. as far as the output stage of th e amplifier is concerned, r f + r g appear in parallel with r l for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently r f also has a minimum value that should not be exceeded for optimum performance. ?for a v = +1, r f = 0 is optimum ?for a v = +2, r f between 300 and 1k is optimum video performance for good video signal integrity, an amplifier is required to maintain the same output impedance and frequency response as dc levels are changed at the output. this can be difficult when driving a standard video load of 150 because of the change in out put current with dc level. a look at the differential gain and differential phase curves will help to obtain optimal performance. curves are provided for a v = +1 and +2, and r l = 150 and 10k . as with all video amplifiers, there is a common mode sweet spot for optimum differential gain/differential phase. for example, with a v = +1 and r l = 150 and the video level kept between 1v and 3v, the amplifier will provide dg/dp performance of 0.17%/0.07. th is condition is representative of using the amplifier as a buffer driving a dc coupled, double terminated, 75 coaxial cable. driving high impedance loads, such as signals on computer video cards gives much better dg/dp performance. for a v = 1, r l = 10k , and the video level kept between 1v and 3v, the dg/dp are 0.03%/0.02. short-circuit current limit the el4501 video amplifier has no internal short circuit protection circuitry. short ci rcuit current of 90ma sourcing and 65ma sinking typically will flow if the output is shorted midway between the rails. if the output is shorted indefinitely, the power dissipated could easily increase the die temperature such that the pa rt will be destroyed. maximum reliability is maintained if the output current never exceeds 50ma. this limit is set by internal metal interconnect limitations. obviously, short ci rcuit conditions must not be allowed to persist or internal metal connections will be damaged or destroyed. driving cables and capacitive loads the el4501 video amplifier can drive 39pf loads in parallel with 150 with 5db of peaking. for less peaking in theses applications a small series resistor of between 5 and 50 can be placed in series with the output. however, this will obviously reduce the gain slightly . if your gain is greater than 1, the gain resistor r g can be adjusted to make up for any lost gain caused by the additi onal output resistor. peaking may also be reducing by adding a ?snubber? circuit at the output. a snubber is a resistor in series with a capacitor, 150 and 100pf being typical values. the advantage of a snubber is that it does not draw dc load current. when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, the back-termination series resistor decouples the video amplifier from the cable and enables extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resistor. again, a small series resistor at th e output can reduce peaking. video sync separator the el4501 includes an advanced sync separator, which is used to generate the dc-restore control signal and seven major sync outputs. the advanced sync separator operates at a 5v dc (pin vsd) single-supply voltage. the input signal source is composite video with levels of 0.5v p-p to 2.0v p-p . el4501
18 low jitter, temperature-stable timing signals are generated using a master time-base, embedded within the system. line rate is adjustable from 10khz to 135khz using a single external resistor (r freq ). an integrated, pin-selectable digital filter tracks line rate and rejects high frequency noise and video artifacts, such as color burst. in addition to the digital filter, a window-based, time qualification scheme is employed to improve recovered signal quality. during loss of signal, all outputs are blanked to prevent output chatter caused by input noise. the maximum total source impedance driving the sync in pin should be 1k or lower. source impedances greater than 1k may reduce the ability of the el4501 to reliably recover the sync signal. composite sync output the composite sync output is a reproduction of the signal waveform below the composite video black level, with the video completely removed. the composite video signal is ac-coupled to sync in (pin 9). the video signal passes through a comparator whose th reshold is controlled by the slice mode pin. the output of the comparator is buffered to the composite output (pin 11) as a cmos logic signal. horizontal sync output the horizontal circuit triggers on the falling edge of the sync tip of the input composite video signal and produces a horizontal output with pulse widths about 12 times the internal oscillator clock. for ntsc video input, the pulse width of the horizontal sync is 1.5s, with the digital filter selected. the half line pulses present in the input signal during vertical blanking are removed with an internal 2h-eliminator circuit. vertical sync output a low-going vertical sync pulse is generated during the start of the vertical cycle of the in coming composite video signal. the vertical output pulse is started on the first serration pulse in the vertical interval and is ended on the second rising edge during the vertical serration phase. in the absence of vertical serration pulses, a vertical sync pulse will be forced out after the vertical sync default delay time, approximately 31s after the last falling edge of the vertical pre-equalizing pulse for r freq = 130k . back porch output in a composite video signal, the chroma burst is located on the back porch of the horizontal blanking period and is also the black level reference for the subsequent video scan line. the back porch is triggered from the rising edge of the sync tip. the pulse width of the back porch is about 29 times the internal oscillator clock cycle. for the ntsc video input, the pulse width of the back porch is about 3.5s. in el4501, the back porch pulse controls the sample and hold switch of the dc-restored loop. odd and even output for a composite video signal t hat is interlaced, there is an odd field that includes all the odd lines, and an even field that consists of the even lines. the odd and even circuit tracks the relationship of the horizontal pulses to the leading edge of the vertical output and will swit ch on every field at the start of vertical sync pulse inte rval. odd/even, pi n 14 is high during the odd field and low during the even field. sync amplitude output the output voltage at the sync amp output (pin 17) is about 2 times the sync tip voltage. this signal can be used for agc applications. when there is no sync signal at the input, the sync amp output is 0v. loss of sync output loss of video signal can be detected by monitoring the los output at pin 10. los goes low indicating the el4501 has locked to the right line rate. los goes high indicating the el4501 is out of lock. when there is loss of sync, all the sync outputs go high, except odd/even. digital filter operation the el4501 contains a user-sel ectable digital filter which tracks the line rate and rejects high frequency noise and video artifacts, such as color bu rst. basically, the digital filter delays all signals and filters out the pulses which are shorter than the filters delay time. the digital filter greatly reduces the jitters in the outputs. with t he digital filter on, the jitter at the composite sync output is only 2ns. figure 39 shows the jitter at the output when the digi tal filter is selected. however, the output waveforms will be de layed from 150ns to 300ns due to this filter. refer to the performance curves for details. applying logic high to the fsel pin, the digital filter is enabled. applying a logic low to the fsel pin, the digital filter is disabled. r freq an external r freq resistor, connected from pin 7 to ground, produces a reference current that is used internally as the timing reference for all the sync output delay time and output pulse widths. decreasing the value of r freq increases the reference current and frequency of the internal oscillator, ch2=2v/div m=2ns figure 39. jitter at the outputs with fsel=1 el4501
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com which in turn decreases the reference time and pulse width. a higher frequency video input requires a lower r freq value. the line rates vs r freq performance curve shows the variation of line rate with r freq . slice mode and operation with vcrs normally the signal source for the el4501 is assumed to be clean and relatively noise free. if that is the case, the slice mode pin (pin 16) should be connected to ground, which sets the slice level to 50% of the sync tip. some signal sources may have excessive video peaking, causing high frequency video and chroma components to extend below the black level reference, such as vcr signals which generate lots of head switching noise. in this case, the slice mode pin should be connected to logic high which sets the slice level to a fixed 100mv above the sync tip. also, a single pole chroma filter is required at the composite video input to increase the s/n ratio of the incoming noisy video signal. when the source impedance is low, typically 75 , a 620 resistor in series with the source and 470pf capacitor to ground will form a low pass filter with a roll-off frequency of about 550khz. this bandwidth sufficiently attenuates the 3.58mhz (ntsc) or 4.43mhz (pal) color burst signal and high frequency spikes, yet pa sses the sync pulse portion without appreciable attenuation. the chroma filter will increase the propagation delay from the composite sync input to the outputs. applying a chroma filter, setting the slice mode pin and fsel pin to high greatly improve the noise immunity performance in vcr applications. output drive capability the outputs of the sync separator are not designed to drive heavy loads. for a 5v vds, if the output is driving 5k load to ground, the output high voltage is about 4.9v. if the output is driving 500 load, the output high voltage is down to 4.2v. general power dissipation with the high output drive capability of the el4501 video amplifier, it is possible to exceed the 125c absolute maximum junction temperature under certain load current conditions. it is important to calculate the maximum junction temperature for a given application to determine if load conditions or package type need to be modified for the amplifier to remain in its safe operating region. the maximum power dissipation allowed in a package is determined according to: where: ?t jmax = maximum junction temperature (125c) ?t amax = maximum ambient temperature (85c) ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by an ic is the product of total quiescent supply current and power supply voltage, plus the power in the ic due to the load. assume no load at the sync separator outputs: where: ?v s = supply voltage ?v sd = digital supply ?i smax = maximum supply current ?i sdmax = maximum digital supply current ?v out = maximum output voltage ?r l = load resistance tied to ground board layout as with any high frequency device, good printed circuit board layout is necessary for optimum performance. ground plane construction is highly recommended. lead lengths should be as short as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. in normal operation, where the gnd pin is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor from v s to gnd will suffice. to reduce cross talk between the analog signal path and the embedded sync separator, a separate digital supply pin, v sd is included on the el4501. this pin should be bypassed in a similar manner to v s . for additional isolation a ferrite bead may be added in line with the supply connections to both pins. for good ac performance, parasitic capacitance should be kept to a minimum. use of wire wound resistors should be avoided because of their additional series inductance. p dmax t jmax - t amax ja -------------------------------------------- - = p dmax v s i smax v sd i sdmax v ( s - v out ) v out r l --------------- - + + = el4501

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